Datasheet can be found here: usb97c202.html
The ide controller hasn’t the same endianness as the cpu.
Sector size is 512 (0×200) bytes.
| Index | Name | |
|---|---|---|
| d0 | data read | |
| d2 | ||
| d4 | SC | Sector count |
| d6 | SN | Sector number |
| d8 | CL | Cylinder? low |
| da | CH | Cylinder? high |
| dc | DH | command register ? |
| de | ST | status register |
| ec | AS | |
| f0 |
| bit | |
|---|---|
| 0-3 | lba high nibble |
| bit | name | low | high | comment |
|---|---|---|---|---|
| 0 | ERR | no error | error | should be clear |
| 1 | ||||
| 2 | ||||
| 3 | DRQ | no data pending | data pending | |
| 4 | ||||
| 5 | DF | should be clear? | ||
| 6 | ||||
| 7 | BSY | idle | busy | should be clear? |
This is done many 100h times, result laid out at 207A00→207BFF
IDE register read: f0 -> 0
Check registers. We check if we read what is written to regs.
IDE register read: de -> 0 IDE register write: d4 <- 55 IDE register write: d6 <- aa IDE register write: d8 <- 0 IDE register write: da <- ff IDE register read: d4 -> 55 IDE register read: d6 -> aa IDE register read: d8 -> 0 IDE register read: da -> ff IDE register read: de -> 0 IDE register write: d4 <- aa IDE register write: d6 <- 55 IDE register write: d8 <- ff IDE register write: da <- 0 IDE register read: d4 -> aa IDE register read: d6 -> 55 IDE register read: d8 -> ff IDE register read: da -> 0 IDE register read: ec -> 0
I assume the following is the bulk of hard reset
IDE register write: dc <- a0 IDE register read: ec -> 0 IDE register read: ec -> 0 IDE register read: ec -> 0 IDE register read: ec -> 0 IDE register write: ec <- e IDE register read: ec -> e IDE register read: ec -> e IDE register read: ec -> e IDE register read: ec -> e IDE register read: ec -> e IDE register read: ec -> e IDE register read: ec -> e IDE register read: ec -> e IDE register read: ec -> e IDE register read: ec -> e IDE register read: ec -> e IDE register read: ec -> e IDE register write: ec <- a IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: de -> 0 IDE register write: dc <- a0 IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a
Soft reset. The values read MUST be as follows. (I assume hard reset has done the init.)
IDE register write: dc <- a0 IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: d4 -> 1 IDE register read: d6 -> 1 IDE register read: d8 -> 0 IDE register read: da -> 0 IDE register read: de -> 0
Another operation. Again, the values read MUST be the same as those written, for d2 through dc.
IDE register write: ec <- a IDE register write: d2 <- 0 IDE register write: d4 <- 1 IDE register write: d6 <- 0 IDE register write: d8 <- 0 IDE register write: da <- 0 IDE register write: dc <- a0 IDE register read: ec -> a IDE register read: d4 -> 1 IDE register read: d6 -> 0 IDE register read: d8 -> 0 IDE register read: da -> 0 IDE register read: dc -> a0
Another operation. Here, de is checked.
IDE register write: de <- ec IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: de -> 8
Data is read (100h words): Ide internal configuration data
IDE register read: d0 -> 0
I assume this finishes the data transfer operation:
IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: ec -> a IDE register read: de -> 0